搜索资源列表
single-clock-CPU
- 单时钟周期CPU，verilog语言编写，quartusII运行-A single clock cycle CPU
pipelined_computer
- 基于de2-board的汇编以及verilog的五段流水线CPU代码，适合新手学习-Based on the de2-board assembler, and the five-stage pipelined CPU verilog code, suitable for novice learning
code
- cpu的主要功能部件verilog简单代码-main features of cpu verilog simple code
ARM-Verilog-HDL-IP-CORE
- ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。-ARM processor IP core, written in verilog processor and CPU architecture knowledge.
cpu
- 用verilog语言写的简单cpu，在处理器功能和结构上，对于初学者有很大帮助。-Verilog language write simple cpu, processor function and structure of great help for beginners.
CPU-implementation-in-verilog
- 用verilogHDL实现CPU各项功能-The implementation of CPU funtions based on verilogHDL
CPU
- 流水线简单CPU设计，基于简单的数字系统设计，为verilog语言，电路设计基于基本的数字电路-Pipelined CPU design, design of digital system based on a simple, Verilog language, based on the basic digital circuit design
RISC-CPU
- 精简指令集RISC-CPU 可以实现阶乘运算 verilog代码编写 含有测试平台-Reduced instruction set RISC-CPU test platform can implement written in the factorial operator verilog code contains
System-Verilog-and-HDL-skills
- 这个教程讲了如何用SystemVerilog写一个CPU，这个教程是和视频专辑http://i.youku.com/u/UMTExNzExOTgw/videos一起使用的，而且里面讲了一些FPGA的逻辑设计技巧-This tutorial about how to use SystemVerilog write a CPU, this tutorial is used in conjunction with, and the video album http://i.youku.com/u/UM
cpu
- 用system verilog写的一个arm处理器原代码。-Write an ARM processor system verilog source code.
RISC-CPU
- 精简指令集 CPU 通过仿真验证正确 (使用之前务必看readme文件，和结构图!) 1. 此cpu是夏宇闻 verilog数字系统设计教程中最后一章的例程。 2. 学习时务必先搞明白框图原理，和数据流动！！！ 3. 牢记主状态机中一条指令周期中传输的16bit=3bit指令+13bit地址。 4. 理解数据总线，和地址总线。区分数据和地址。 5. 仔细调试，因为书中有很多小错误。 程序经过quartusii编译通过，另外经过modelsim仿真正确。-RISC
lab-1-ALU-design-with-Verilog-HDL
- cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
lab-4-cpu-design-with-Verilog-HDL
- 用veriloghdl 编写的cpu代码，modusim仿真通过，包括原理图和代码，以实验报告形式写出-CPU code, written in veriloghdl modusim simulation through, including the principle diagram and code, in the form of a lab report write
CPU
- 东南大学VHDL课程CPU设计 Verilog语言-Southeast University, CPU design Verilog language VHDL course
pipelined-CPU
- verilog实现的流水线CPU 通过仿真和下载验证-verilog achieve pipelined CPU verified by simulation and downloads
avr_core_latest.tar
- avr cpu verilog 源码实现，欢迎下载使用-avr cpu verilog source implementations are welcome to download
CPU
- 基于FPGA控制的ASIC CPU系统设计，全是用VERILOG代码编写，可以做加减乘除运算 -FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done
singleCPU
- 用Verilog实现的单周期CPU,分别实现I型、R型、J型指令，并包含测试文件。可供参考。-With single-cycle CPU Verilog implementation, respectively, to achieve type I, R, J-type instruction, and includes test files. For reference.
Verilog-language--de-CPU
- 基于verilog语言的FPGA开发，平台在QuartusII上，对SDRAM的读写-Verilog language based FPGA development platform on QuartusII, the SDRAM read and write
88RISC-CPU
- cpu设计能在quartus上运行 用verilog语言-a cpu program use verilog on quartus